This invention relates to electrical interconnection of integrated circuit chips and, particularly, to stackable integrated circuit devices suited for vertical interconnection.
Interconnection of die with one another in a stack of die (“die-to-die”) or of a die or a die stack with a substrate (“die-to-substrate”) presents a number of challenges. For example, the integrated circuitry is situated on an “active side” of the die, and exposed pads are situated on the active side of the die for electrical interconnection with other die or with a substrate. When die are stacked, one die in the stack may obscure the pads on another die, making them inaccessible for interconnection, particularly where die having the same or similar dimensions are stacked one over another.
Various kinds of die interconnection have been proposed, including among others flip-chip interconnect, wire bond interconnect, and tab bond interconnect.
Where wire bond interconnect is employed in a stacked die assembly, the wire bonds may be formed to connect pads on the active side of a first die before an additional die is stacked over it. A spacer is typically provided upon the active side of the first die, to prevent interference by the second die with the wire loops on the first die.
Approaches to vertical interconnection of die, other than by wire bonds, bumps, or tabs are described, for example, in U.S. Pat. No. 5,675,180 and its progeny; and, for example, in U.S. Pat. No. 7,215,018 and, for example, in U.S. application Ser. No. 11/097,829.
Particularly, for example, U.S. application Ser. No. 11/097,829 describes “off-die” interconnection, employing interconnection terminals electrically connected to peripheral sites on the die and projecting beyond the die edge; interconnection of the die is made by electrically conductive polymer elements into which the projecting parts of the interconnection terminals extend.
Some die as provided have die pads along one or more of the die margins, and these may be referred to as peripheral pad die. Other die as provided have die pads arranged in one or two rows near the center of the die, and these may be referred to as center pad die. The die may be “rerouted” to provide a suitable arrangement of interconnect pads at or near one or more of the edges of the die.
It can be advantageous to carry out certain processing steps at the wafer level, prior to singulation of the die.
U.S. application Ser. No. 11/016,558 describes methods for providing an electrically insulative conformal coating on all surfaces (active or front side, back side, and sidewalls) of individual singulated semiconductor die.